1. Field of the Invention
This invention relates to a processor and, in particular, a microprogram controlled processor. More particularly, the invention relates to a processor having improved facilities for generating system address words having a specified bit width from data words having a lesser bit width.
2. Description of the Prior Art
Stored program controlled systems often comprise a processor, a random access system memory external to the processor, peripheral equipment which performs the useful work of the system, a data bus and an address bus. The data bus is typically used for the bidirectional exchange of information between the processor and the memory as well as between the processor and the peripheral equipment. The address bus is used for the unidirectional transmission of address words from the processor to the memory and the peripheral equipment. The address words control the reading or writing of memory as well as the transmission of control signals between the processor and the peripheral equipment.
Memory address words are normally generated by incrementing a program counter in the processor to access the memory location following that associated with a currently executed instruction. At other times, such as on a branch or a jump instruction, the processor receives information over the data bus from the memory specifying the address of the next instruction that is to be executed. This transmission of address information to the processor presents no problem if the bit width of the data bus equals or exceeds that of the address bus. However, the transmission of address information is more complex if the bit width of the data bus is less than that of the address bus. For example, let it be assumed that the data bus has 16 conductors, that the address bus has 20 conductors, and that addresses are 20 bits wide. In this case, the reception of a single word over the data bus obviously cannot specify a 20-bit address. It is necessary in such circumstances to transmit address information to the processor in the form of two data words which together contain the required 20 address bits.
The above method of generating address words has heretofore increased processor cost and complexity since special circuitry is required to steer the bits of each received data word to the appropriate processor elements so that the received bits together represent the required 20-bit address. Let it be assumed that four bits of a first 16-bit data word represent the four most significant bits of a 20-bit address; let it also be assumed that these four bits are in the four least significant bit positions of the first data word. Let it further be assumed that all 16 bits of a second data word represent the 16 least significant bits of the 20-bit address. With these assumptions, the processor must have facilities to receive the four address bits in the first data word and to steer these four bits into the processor elements that store the four most significant address bits. These facilities must also steer the 16 bits of the data second word into the processor elements that store the 16 least significant address word bits.
There are many ways of performing the abovementioned operation. The most obvious is the use of gates, steering circuits, multiplexors, etc. Although this would permit the processor to generate the required address words, the use of this special circuitry would increase the complexity and cost of the processor.
It is therefore a problem to provide a processor with facilities for generating address words from data words of a lesser bit width without increasing the processor cost and complexity.